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Data Sheet No. PD60292
IRS2166D(S)PbF
PFC + BALLAST CONTROL IC
Features
PFC, ballast control and 600 V half-bridge driver in one IC Critical-conduction mode boost-type PFC Programmable half-bridge over-current protection Programmable preheat frequency Programmable deadtime Programmable preheat time Programmable run frequency End-of-life window comparator pin Internal up/down current-sense fault counter DC bus undervoltage reset Lamp removal/auto-restart shutdown pin Internal bootstrap MOSFET Internal 15.6 V zener clamp diode on VCC Micropower startup (250 A) Latch immunity and ESD protection
Description
The IRS2166D is a fully integrated, fully protected 600 V ballast control IC designed to drive all types of fluorescent lamps. The IRS2166D is based on the popular IR2166 control IC with additional improvements to increase ballast performance. PFC circuitry operates in critical conduction mode and provides high PF, low THD, and DC bus regulation. The IRS2166D features include programmable preheat and run frequencies, programmable preheat time, and programmable end-of-life protection. Comprehensive protection features such as protection from failure of a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as well as an automatic restart function, have been included in the design.
System Features
Improved VBUS regulation voltage tolerance Increased SD pin shutdown voltage threshold hysteresis Changed EOL pin internal 2.0 V bias to a +/-10 A OTA Internal bootstrap MOSFET
Packages
16-Lead PDIP IRS2166DPBF
16-Lead SOIC IRS2166DSPbF
Application Diagram (Typical Only)
LPFC DPFC RBUS
F1
RV1 L1 C1 BR1 RVDC CVDC CBUS CPH CPH RT RT RPH C2 CT RPH CT VBUS HO VS VB VCC CVCC2 RL O RLIM DSD RSD CBOOT RH O
L N
RSUPPLY
1 2 3 4 5 6
16 15 14 13 12 11 10 9
MHS
LRES
CDC
IRS2166D
GND
CY
CSNUB DCP2
RDC
REOL1 CRES REOL2 ML S
CVCC1 COM LO CS
CCOMP COMP RZX ZX PFC
RPU DCP1
7 8
REOL3
SD/EOL
DCOMP
IC BALLAST CEOL CSD1 CSD2
CCS
RCS
REOL4
MPFC
RPFC
Note: Thick traces represent high-frequency, high-current paths. Lead lengths should be minimized and power and IC grounds should be separated to avoid high-frequency noise problems.
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IRS2166D(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VB VS VHO VLO VPFC IO,MAX VBUS VCPH VRT VRPH IRT IRPH VCT ICOMP IZX ICC VSD/EOL ISD/EOL VCS ICS dV/dt PD RJA TJ TS
Definition
High-side floating supply voltage High-side floating supply offset voltage High-side floating output voltage Low-side output voltage PFC gate driver output voltage Maximum allowable output current (HO, LO, PFC) due to external power transistor miller effect VBUS pin voltage CPH pin voltage RT pin voltage RPH pin voltage RT pin current RPH pin current CT pin voltage COM pin current ZX pin current VCC pin current (see Note 1) SD/EOL pin voltage SD/EOL pin current CS pin voltage CS pin current Allowable VS offset voltage slew rate Package power dissipation @ TA +25 C PD = (TJMAX-TA)/RJA Thermal resistance, junction to ambient Junction temperature Storage temperature (16-Pin DIP) (16-Pin SOIC) (16-Pin DIP) (16-Pin SOIC)
Min.
-0.3 VB - 25 VS - 0.3 -0.3 -0.3 -500 -0.3 -0.3 -0.3 -0.3 -5 -5 -0.3 -5 -5 -25 -0.3 -5 -0.3 -5 -50 ---------55 -55
Max.
625 VB + 0.3 VB + 0.3 VCC + 0.3 VCC + 0.3 500 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 5 5 VCC + 0.3 5 5 25 VCC + 0.3 5 VCC + 0.3 5 50 1.8 1.4 70 82 150 150
Units
V
mA
V
mA V mA V mA V mA V/ns W C/W
C
TL Lead temperature (soldering, 10 seconds) --300 Note 1: This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6 V. This supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the electrical characteristics section.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
VB-VS VS VCC ICC CT ISD/EOL ICS IZX
Definition
High side floating supply voltage Steady state high-side floating supply offset voltage Supply voltage VCC supply current (see Note 2) CT pin capacitance SD/EOL pin current CS pin current ZX pin current
Min.
VBSUV+ -1 VCCUV+ Note 2 220 -1
Max.
VCLAMP 600 VCLAMP 20 --1
Units
V mA pF mA
TJ Junction temperature -25 125 C Note 2: Enough current should be supplied into the VCC pin to keep the internal 15.6 V zener clamp diode on this pin regulating its voltage, VCLAMP.
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Electrical Characteristics
VCC = VBS = VBIAS=14 V +/- 0.25 V, VCPH=VSD/EOL=VCOMP=VCS=VBUS=VZX=0.0 V, RT = RPH = 39.2 k, CLO = CHO = CPFC = 1000 pF, CT = 470 pF, TA =25 C unless otherwise specified. See state diagram for MODE.
Symbol
Supply Characteristics VCCUV+ VCCUVVUVHYS IQCCUV IQCC IQCCFLT ICC,RUN VCLAMP IQBS0 IQBS1 VBSUV+ VBSUVILKVS
Definition
VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage lockout hysteresis UVLO mode VCC quiescent current Quiescent VCC supply current Fault quiescent VCC supply current VCC current at RUN frequency VCC zener clamp voltage Quiescent VBS supply current Quiescent VBS supply current VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VS offset supply leakage current
Min
11.5 9.5 1.5 --------14.6 ----8.0 7.0 ---
Typ
12.5 10.5 2.0 250 4.3 600 5.0 15.6 30 50 9.0 8.0 ---
Max
13.5 11.5 3.0 500 5.1 900 --16.6 70 90 10.0
Units
Test Conditions
VCC rising from 0 V, CT = COM
V
VCC falling from 14 V, CT = COM CT = COM VCC = 8 V, CT = COM CT = COM MODE = FAULT MODE=RUN COMP=2 V, toff,PFC=2 s ICC = 10 mA VHO = VS VHO = VB VBS rising from 0 V VBS falling from 14 V
A mA A mA V
Floating Supply Characteristics A
V 9.0 50 A
VB = VS = HO = 600 V MODE = RUN VVBUS = 3.5 V MODE = RUN VVBUS = 4.5 V
PFC Error Amplifier Characteristics ICOMP,SOURCE OTA error amplifier output current sourcing ICOMP,SINK VCOMPOH VCOMPOL OTA error amplifier output current sinking OTA error amplifier output voltage swing (high state) OTA error amplifier output voltage swing (low state) VBUS internal reference voltage (guaranteed by design) VBUS over-voltage comparator positive going threshold VBUS over-voltage comparator negative going hysteresis ZX pin positve edge triggered threshold voltage ZX pin comparator hysterisis ZX pin clamp voltage (high state) PFC watch-dog pulse interval 20 -45 12.0 200 30 -35 12.5 300 40 A -25 13.0 400 V mV
PFC Control Characteristics VVBUSREG VVBUSOV+ VVBUSOVVZX VZXHYS VZXclamp tWD 3.9 4.1 4.0 1.5 100 5.7 150 4.0 4.3 4.15 2.0 300 6.7 400 4.1 4.5 V 4.3 2.5 500 7.7 500 mV V s IZX = 5 mA, CT=COM VZX = 0 V, VCOMP = 2.0 V CT=COM CT=COM VCOMP=4.0 V
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IRS2166D(S)PbF
Electrical Characteristics (cont'd)
VCC = VBS = VBIAS=14 V +/- 0.25 V, VCPH=VSD/EOL = VCOMP= VCS= VBUS = VZX =0.0 V, RT = RPH = 39.2 k, CLO = CHO = CPFC = 1000 pF, CT = 470 pF, TA=25 C unless otherwise specified. See state diagram for MODE.
Symbol
Definition
Min
2.7 ------------13.2 40 9 73 40 --0.7 0.7 7.8 4.1 ------2.6 --1.075 70 4.5 2.7 --1.8 ----2.7 0.9 -------
Typ
3.0 COM VCC 120 50 180 260 13.7 55 12 76 43 50 1.0 1.0 8.4 4.6 10.8 12.0 0.1 3.6 0 1.20 100 5.0 3.0 450 2.0 10 10 3.0 1.0 1 0 0
Max
3.3 ----220 100 ----------81 46 --1.5 1.5 9.0 5.1 ------4.6 --1.325 140 5.5 3.3 --2.2 ----3.3
Units
V
Test Conditions
CT=COM
PFC Protection Circuitry Characteristics VVBUSUVVBUS pin undervoltage reset threshold Gate Driver Output Characteristics (HO, LO and PFC pins) VOL VOH tr tf I0+ I0VB,ON IB,CAP IB,10V fPH fRUN D td,LO td,HO VCT+ VCTVCPHEOP VCPHRUN IRPHLK ICPH VCPHFLT VCSTH+ nEVENTS VSDTH+ VSDTHVSD,delay VEOLBIAS IEOL,SRC IEOL,SNK VEOLTH+ VEOLTHVEOL,delay VCTFLT VCPHFLT Low-level output voltage, LO, HO, PFC High-level output voltage, LO, HO, PFC Turn-on rise time Turn-off fall time Source current Sink current VB when the bootstrap FET is on VB source current when FET is on VB source current when FET is on Preheat half-bridge oscillator frequency Run half-bridge oscillator frequency Oscillator duty cycle LO output deadtime HO output deadtime CT pin rising threshold voltage CT pin falling threshold voltage CPH pin end of preheat threshold voltage CPH pin run mode threshold voltage RPH pin leakage current CPH pin charging current CPH pin voltage in fault mode CS pin over-current sense threshold CS pin fault counter number of events SD pin rising non-latched shutdown threshold lt SD pin falling reset threshold voltage Delay from VSDTH+ until LO goes low EOL pin bias voltage EOL pin internal OTA source current EOL pin internal OTA sink current EOL pin rising latched shutdown threshold (active during RUN MODE) EOL pin falling latched shutdown threshold (active during RUN MODE) Delay from VEOLTH+ until LO goes low CT pin fault mode voltage CPH pin fault mode voltage
V ns mA
Bootstrap FET Characteristics V mA CBS=0.1 F VB=10 V MODE=PREHEAT MODE=RUN, CPH=13 V
Ballast Control Oscillator Characteristics kHz
% s V
Ballast Control Preheat Characteristics V CT=COM, IRPH<2 A VBUS=VCC, CT=COM, VSDEOL=3.5 V, MODE=RUN CPH=5 V MODE = FAULT
A V V
Ballast Control Protection Circuitry Characteristics MODE=PREHEAT, VBUS=0 V V ns V A SD = VEOLBIAS + 0.5 V MODE=RUN, CT=COM VBUS=4.0 V, CPH=13 V MODE=RUN, CT=COM, CPH=13 V MODE=FAULT CT=COM
V 1.1 ------s V
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IRS2166D(S)PbF
Schematic Block Diagram
VCC
13
S1 15.6 V
COM
12
VCC
RT 3
S2 40 K
R Soft Start R T R 3 uA S4 R R R Driver Logic
Bootstrap Control HighSide Driver
14
VB
16
HO
CT 5
RDT 3.0K S3 VTH
Q Q
15
VS
RPH 4
S5 Fault Counter LowSide Driver Fault Logic RUN
CPH 2
S6
11
LO
VCC S R1 R2 Q 3.0 V 2V Q
10
1.25 V
CS
Ballast Control PFC Control
3.0 V S R Q Q
1.0 V VCC UVLO Q S R1 Q R2 5V
9
SD/EOL
VBUS 1
4.0 V
OVP Gain
4.3 V
3V
VCC
COMP
8
RS3 S RS2 SQ R Q Q 400 us Watch Dog Timer RS4
6
PFC
4.0 V
RS1
3.5 V
R1 R2 Q S R1 R2 Q Q
S R
Q Q
ZX 7
6.7 V 1.0 V
Please Note: All values shown in block diagram are typical values only
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IRS2166D(S)PbF
State Diagram
Power Turned On
UVLO Mode
1/ -Bridge Off 2 IQCCUV 250A CPH = 0V CT = 0V PFC Off
VCC < 10.5 V (VCCUV-) (Power Turned Off) SD/EOL > 5.0V (VSDTH+) (Lamp Removal)
SD/EOL > 5.0 V (VSDTH+) (Lamp Removal) or VCC < 10.5 V (VCCUV-) (Power Turned Off)
VCC > 12.5 V (VCCUV+) and SD/EOL < 3.0 V (VSDTH-)
FAULT Mode
Fault Latch Set 1/ -Bridge Off 2 IQCCFLT 600A CPH = 0 V CT = 0 V PFC Off
PREHEAT Mode
1
CS > 1.2 V (VCSTH+) for 100 events (nEVENTS)
/2-Bridge oscillating @ fPH RPH // RT CPH Charging PFC Enabled (High Gain) CS Enabled Fault Counter Enabled
CPH > 10.8 V (VCPHEOP)
IGNITION Mode
CS > 1.2 V (VCSTH+) for 100 events (nEVENTS) RPH Open fPH ramps to fRUN CPH charging PFC = High Gain Mode CS Enabled Fault Counter Enabled
CPH > 12.0 V (VCPHRUN) CS > 1.2 V (VCSTH+) (single event) or SD/EOL < 1.0 V (VEOLTH-) RUN Mode or RPH = Open SD/EOL > 3.0 V (VEOLTH+) 1/2-Bridge Oscillating @fRUN PFC = Low Gain Mode VBUS UV Threshold Enabled CS Enabled Fault Counter Disabled
VBUS < 3.0 V Discharge (VBUSUV) VCC to UVLO
All values are typical. Applies to application diagram on page 1.
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IRS2166D(S)PbF
Lead Assignments & Definitions
VBUS HO
1
CPH
16
VS
Pin # Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBUS CPH RT RPH CT COMP ZX PFC SD/EOL CS LO COM VCC VB VS HO
Description
DC bus sensing input Preheat timing capacitor Oscillator timing resistor Preheat frequency timing resistor Oscillator timing capacitor PFC error amplifier compensation PFC zero-crossing detection PFC gate driver output Shutdown/end of life densing circuit Half-bridge current sensing input Low-side gate driver output IC power & signal ground Logic & low-side gate driver supply High-side gate driver floating supply High voltage floating return High-side gate driver output
2
15
3
RPH
IRS2166D
RT
VB
14
VCC
4
CT
13
COM
5
COMP
12
LO
7 6
ZX
11
CS
7
PFC
10
SD/EOL
8
9
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Timing Diagrams Ballast Section
VCC
15.6V UVLO+ UVLO-
VCC
CPH
f run
FREQ
fph
SD
HO LO CS
1.25V
SD > 5.1V
FAULT
IGN
IGN
UVLO
PH
PH
RUN
UVLO
50 events of CS>1.25V
RT
RT
OPEN
RT
RPH
RPH
OPEN
RPH
CT
CT
CT
HO
HO
HO
LO
LO
1.25V
LO
CS
CS
CS
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IRS2166D(S)PbF
I. Ballast Section Functional Description Undervoltage Lock-Out Mode (UVLO)
The undervoltage lock-out mode (UVLO) is defined as the state the IC is in when VCC is below the turn-on threshold of the IC. To identify the different modes of the IC, refer to the State Diagram shown on page 7 of this document. The IRS2166D undervoltage lock-out is designed to maintain an ultra low supply current of 250 A (IQCCUV), and to guarantee the IC is fully functional before the high and low side output drivers are activated. Fig. 1 shows an efficient supply voltage using the start-up current of the IRS2166D together with a charge pump from the ballast output stage (RSUPPLY, CVCC, DCP1, and DCP2).
VBUS(+) R SUPPLY D BOOT 16 15 14 13 12 11 HO VS VB VCC COM LO C BOOT C VCC C SNUB M1 Half-Bridge Output
VC1
CVCC DISCHARGE VUVLO+
VHYST INTERNAL VCC ZENER CLAMP VOLTAGE
VUVLO-
DISCHARGE TIME
CHARGE PUMP OUTPUT RSUPPLY & CVCC TIME CONSTANT
t
Fig. 2: Supply capacitor (CVCC) voltage
Preheat Mode (PH)
The preheat mode is defined as the state the IC is in when the lamp filaments are being heated to their correct emission temperature. This is necessary for maximizing lamp life and reducing the required ignition voltage. The IRS2166D enters preheat mode when VCC exceeds the UVLO positive-going threshold VCCUV+. HO and LO begin to oscillate at the preheat frequency with 50% duty cycle and with a deadtime which is set by the value of the external timing capacitor, CT, and internal deadtime resistor, RDT. Pin CPH is disconnected from COM and an internal 3.6 A (ICPH) current source (Fig. 3) charges the external preheat timing capacitor on CPH linearly. The over-current protection on pin CS is enabled during preheat. The preheat frequency is determined by the parallel combination of resistors RT and RPH, together with timing capacitor CT. CT charges and discharges between 1/3 (VCT-) and 3/5 (VCT+) of VCC (see Timing Diagram, page 9). CT is charged exponentially through the parallel combination of RT and RPH connected internally to VCC through MOSFET S1. The charge time of CT from 1/3 to 3/5 VCC is the on-time of the respective output gate driver, HO or LO. Once CT exceeds 3/5 VCC, MOSFET S1 is turned off, disconnecting RT and RPH from VCC. CT is then discharged exponentially through an internal resistor, RDT, through MOSFET S3 to COM. The discharge time of CT from 3/5 to 1/3 VCC is the deadtime (both off) of the output gate drivers, HO and LO. The selected value of CT and RDT program the desired deadtime (see Design Equations, page 15, Equations 1 and 2). Once CT discharges below 1/3 VCC, MOSFET S3 is turned off, disconnecting RDT from COM, and MOSFET S1 is turned on, connecting RT and RPH again to VCC. The frequency remains at the preheat frequency until the voltage on pin CPH exceeds 10 V and the IC enters ignition mode. During the preheat mode, both the overcurrent protection and the DC bus undervoltage reset are enabled when pin CPH exceeds 12 V (VCPHRUN).
IRS2166D
M2 D CP1 RCS D CP2
VBUS(-)
Fig. 1: Start-up and supply circuitry The start-up capacitor (CVCC) is charged by current through supply resistor (RSUPPLY) minus the start-up current drawn by the IC. This resistor is chosen to set the line input voltage turn-on threshold for the ballast. Once the capacitor voltage on VCC reaches the start-up threshold VCCUV+, and the SD pin is below 3.0 V (VSDTH-), the IC turns on and HO and LO begin to oscillate. The capacitor begins to discharge due to the increase in IC operating current (Fig. 2). During the discharge cycle, the rectified current from the charge pump charges the capacitor above the IC turn-off threshold. The charge pump and the internal 15.6 V (VCLAMP) zener clamp of the IC take over as the supply voltage. The start-up capacitor and snubber capacitor must be selected such that enough supply current is available over all ballast operating conditions. A supply capacitor (CBOOT) comprises the supply voltage for the high side driver circuitry. To guarantee that the high-side supply is charged up before the first pulse on pin HO, the first pulse from the output drivers comes from the LO pin. During undervoltage lock-out mode, the high- and low-side driver outputs HO and LO are both low, pin CT is connected internally to COM to disable the oscillator, and pin CPH is connected internally to COM for resetting the preheat time.
Ignition Mode (IGN)
The ignition mode is defined as the state the IC is in when a high voltage is being established across the lamp necessary for igniting the lamp. The IRS2166D enters ignition mode when the voltage on pin CPH exceeds 10.8 V (VCPHEOP). Pin CPH is connected internally to the
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IRS2166D(S)PbF
VBUS (+)
V BUS (+) VCC
13
R T
RT
3 S4 4
OSC. HalfBridge Driver
16
HO
M1
RT
RT
S 1 3 S 4 4
OSC HalfBridge Driver
16
HO
M1
RPH
R PH
15
VS
HalfBridge Output ILOAD
RPH
R PH
15
VS
HalfBridge Output I LOAD
C T
5 11
CT
CT
5
CT
Fault Logic
LO
M2
11 S 3
1.3V
LO
M2
CS
10
R1 CCS
5uA
5uA
CPH
CCPH
2 12
CPH
RCS
Comp 4
2 12
RCS
COM Load Return
V BUS (-)
CCPH
COM Load Return
IRS2166D
IRS2166D
VBUS (-)
Fig. 3: Preheat circuitry gate of a p-channel MOSFET (S4) (see Fig. 4) that connects pin RPH with pin RT. As pin CPH exceeds 10.8 V (VCPHEOP), the gate-to-source voltage of MOSFET S4 begins to fall below the turn-on threshold of S4. As pin CPH continues to ramp towards VCC, switch S4 turns off slowly. This results in resistor RPH being disconnected smoothly from resistor RT, which causes the operating frequency to ramp smoothly from the preheat frequency, through the ignition frequency, to the final run frequency. The over-current threshold on pin CS will protect the ballast against a non-strike or open-filament lamp fault condition. The voltage on pin CS is defined by the lower half-bridge MOSFET current flowing through the external current sensing resistor RCS. The resistor RCS therefore programs the maximum allowable peak ignition current (and therefore peak ignition voltage) of the ballast output stage. The peak ignition current must not exceed the maximum allowable current ratings of the output stage MOSFETs. Should this voltage exceed the internal threshold of 1.20 V (VCSTH+), the internal fault counter begins counting the number of of sequential over-current faults (see timing diagram). If the number of over-current faults exceeds 50 (nEVENTS), the IC will enter FAULT mode and gate driver outputs HO, LO and PFC will be latched low.
Fig.4: Ignition circuitry
DC Bus Undervoltage Reset
Should the DC bus decrease too low during a brown-out line condition or over-load condition, the resonant output stage to the lamp can shift near or below resonance. This can produce hard-switching at the half-bridge which can damage the half-bridge switches or, the DC bus can decrease too far and the lamp can extinguish. To protect against this, the VBUS pin includes a 3.0 V undervoltage threshold (VBUSUV). Should the voltage at the VBUS pin decrease below 3.0 V, VCC will be discharged below the VCCUV- threshold and all gate driver outputs will be latched low. For proper ballast design, the designer should design the PFC section such that the DC bus does not drop until the AC line input voltage falls below the rated input voltage of the ballast (see PFC section). When correctly designed, the voltage measured at the VBUS pin will decrease below the internal 3.0 V threshold (VBUSUV) and the ballast will turn off cleanly. The pull-up resistor to VCC (RSUPPLY) will then turn the ballast on again when the AC input line voltage increases to the minimum specified value causing VCC to exceed VCCUV+. RSUPPLY should be set to turn the ballast on at the minimum specified ballast input voltage. The PFC should then be designed such that the DC bus decreases at an input line voltage that is lower than the minimum specified ballast input voltage. This hysteresis will result in clean turn-on and turn-off of the ballast.
Run Mode (RUN)
Once the lamp has successfully ignited, the ballast enters run mode. The run mode is defined as the state the IC is in when the lamp arc is established and the lamp is being driven to a given power level. The run mode oscillating frequency is determined by the timing resistor RT and timing capacitor CT (see Design Equations, page 15). Should hard-switching occur at the half-bridge at any time due to an open-filament or lamp removal, the voltage across the current sensing resistor, RCS, will exceed the internal threshold of 1.20 V (VCSTH+) and the fault counter will begin counting (see timing diagram). Should the number of consecutive over-current faults exceed 50 (nEVENTS), the IC will enter fault mode and gate driver outputs HO, LO and PFC will be latched low.
SD/EOL and CS Fault Mode (FAULT)
Should the voltage at the SD/EOL pin exceed 3.0 V (VEOLTH+) or decrease below 1.0 V (VEOLTH-) during run mode, an end-of-life (EOL) fault condition has occurred and the IC enters fault mode. LO, HO, and PFC gate driver outputs are all latched off in the `low' state. CPH is discharged to COM for resetting the preheat time. To exit fault mode, VCC can be decreased below VCCUV- (ballast power off) or the SD pin can be increased above 5.0 V (VSDTH+) (lamp removal). Either of these will force the IC to enter UVLO mode (see State Diagram, page 7). Once
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IRS2166D(S)PbF
50 Pulses
VCC is above VCCUV+ (ballast power on) and SD is pulled above 5.0 V (VSDTH+) and back below 3.0 V (VSDTH-) (lamp re-insertion), the IC will enter preheat mode and begin oscillating again. The current sense function will force the IC to enter fault mode only after the voltage at the CS pin has been greater than 1.20 V (VCSTH+) for 100 (nEVENTS) consecutive cycles of LO. The over-current function at the CS pin (see Fig. 5) will only consecutive cycles of LO. The overcurrent function at the CS pin (see Fig. 5) will only work with over-current events that occur during the LO on-time. If the over-current faults are not consecutive, then the internal fault counter will count back down each cycle when there is no fault present. Should an over-current fault occur only for a few cycles and then not occur again, the counter will eventually count back down to zero. The over-current fault counter is enabled during preheat and ignition modes and disabled during run mode. During run mode, the IC will enter fault mode after a single overcurrent event at the CS pin.
LO
CS
2.0V
Preheat or Ignition Mode
Fault Mode
Fig. 5: CS & LO Waveforms When the switch MPFC is turned on, the inductor LPFC is connected between the rectified line input (+) and (-) causing the current in LPFC to charge up linearly. When MPFC is turned off, LPFC is connected between the rectified line input (+) and the DC bus capacitor CBUS (through diode DPFC) and the stored current in LPFC flows into CBUS. As MPFC is turned on and off at a high-frequency, the voltage on CBUS charges up to a specified voltage. The feedback loop of the IRS2166D regulates this voltage to a fixed value by continuously monitoring the DC voltage and adjusting the on-time of MPFC accordingly. For an increasing DC bus the on-time is decreased, and for a decreasing DC bus the on-time is increased. This negative feedback control is performed with a slow loop speed and a low loop gain such that the average inductor current smoothly follows the low-frequency line input voltage for high power factor and low THD. The on-time of MPFC therefore appears to be fixed (with an additional modulation to be discussed later) over several cycles of the line voltage. With a fixed on-time, and an off-time determined by the inductor current discharging to zero, the result is a system where the switching frequency is free-running and constantly changing from a high frequency near the zero crossing of the AC input line voltage, to a lower frequency at the peaks (Fig. 7).
V, I
II. PFC Section Functional Description
In most electronic ballasts it is necessary to have the circuit act as a pure resistive load to the AC input line voltage. The degree to which the circuit matches a pure resistor is measured by the phase shift between the input voltage and input current and how well the shape of the input current waveform matches the shape of the sinusoidal input voltage. The cosine of the phase angle between the input voltage and input current is defined as the power factor (PF), and how well the shape of the input current waveform matches the shape of the input voltage is determined by the total harmonic distortion (THD). A power factor of 1.0 (maximum) corresponds to zero phase shift and a THD of 0% represents a pure sinewave (no distortion). For this reason it is desirable to have a high PF and a low THD. To achieve this, the IRS2166D includes an active power factor correction (PFC) circuit which, for an AC line input voltage, produces an AC line input current. The control method implemented in the IRS2166D is for a boost-type converter (Fig. 6) running in critical-conduction mode (CCM). This means that during each switching cycle of the PFC MOSFET, the circuit waits until the inductor current discharges to zero before turning the PFC MOSFET on again. The PFC MOSFET is turned on and off at a much higher frequency (>10 kHz) than the line input frequency (50 Hz to 60 Hz).
LPFC (+) DPFC
t
Fig. 7: Sinusoidal line input voltage (solid line), triangular PFC inductor current and smoothed sinusoidal line input current (dashed line) over one half-cycle of the line input voltage When the line input voltage is low (near the zero crossing), the inductor current will charge up to a small amount and the discharge time will be fast resulting in a high switching frequency. When the input line voltage is high (near the peak), the inductor current will charge up to a higher amount and the discharge time will be longer giving a lower switching frequency. The triangular PFC inductor current is then smoothed by the EMI filter to produce a sinusoidal line input current.
DC Bus
+ MPFC (-) CBUS
Fig. 6: Boost-type PFC circuit
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IRS2166D(S)PbF
The PFC control circuit of the IRS2166D (Fig. 8) only requires four control pins: VBUS, COMP, ZX and PFC. The VBUS pin is for sensing the DC bus voltage (via an external resistor voltage divider), the COMP pin programs the on-time of MPFC and the speed of the feedback loop, the ZX pin detects when the inductor current discharges to zero (via a secondary winding from the PFC inductor), and the PFC pin is the low-side gate driver output for MPFC.
LPFC
(+)
DFPC
the off-time and MPFC is turned on again (Fig. 10). The cycle repeats itself indefinitely until the PFC section is disabled due to a fault detected by the ballast section (fault mode), an over-voltage or undervoltage condition on the DC bus, or, the negative transition of ZX pin voltage does not occur. Should the negative edge on the ZX pin not occur, MPFC will remain off until the watch-dog timer forces a turn-on of MPFC for an on-time duration programmed by the voltage on the COMP pin. The watch-dog pulses occur every 400 s (tWD) indefinitely until a correct positive- and negative-going signal is detected on the ZX pin and normal PFC operation is resumed.
RVBUS1 RZX VBUS ZX
COMP
PFC Control
CBUS PFC RPFC MPFC
ILPFC
0
COM DCOMP RVBUS CCOMP
(-)
PFC pin
0
Fig. 8: IRS2166D simplified PFC control circuit The VBUS pin is regulated against a fixed internal 4.0 V reference voltage (VBUSREG) for regulating the DC bus voltage (Fig. 9). The feedback loop is performed by an operational transconductance amplifier (OTA) that sinks or sources a current to the external capacitor at the COMP pin. The resulting voltage on the COMP pin sets the threshold for the charging of the internal timing capacitor (C1) and therefore programs the on-time of MPFC. During preheat and ignition modes of the ballast section, the gain of the OTA is set to a high level to raise the DC bus level quickly and to minimize the transient on the DC bus which can occur during ignition. During run mode, the gain is then decreased to a lower level necessary for achieving high power factor and low THD.
Run Mode Signal Fault Mode Signal
ZX pin
0
Fig. 10: LPFC current, PFC pin and ZX pin timing diagram A fixed on-time of MPFC over an entire cycle of the line input voltage produces a peak inductor current which naturally follows the sinusoidal shape of the line input voltage. The smoothed averaged line input current is in phase with the line input voltage for high power factor but the total harmonic distortion (THD), as well as the individual higher harmonics, of the current can still be too high. This is mostly due to cross-over distortion of the line current near the zero-crossings of the line input voltage. To achieve low harmonics which are acceptable to international standard organizations and general market requirements, an additional on-time modulation circuit has been added to the PFC control. This circuit dynamically increases the on-time of MPFC as the line input voltage nears the zero-crossings (Fig. 11). This causes the peak LPFC current, and therefore the smoothed line input current, to increase slightly higher near the zero-crossings of the line input voltage. This reduces the amount of cross-over distortion in the line input current which reduces the THD and higher harmonics to low levels.
VBUS 1
GAIN 4.0V OTA1 4.3V COMP4 VCC
COMP 6
M1 COMP2 Discharge VCC to UVLOC1
COMP5
RS3 S R Q Q WATCH DOG TIMER RS4 SQ R1 R2 Q
8
PFC
3.0V
M2
ZX 7
7.6V 2.0V
COMP3
Fig. 9: IRS2166D detailed PFC control circuit The off-time of MPFC is determined by the time it takes the LPFC current to discharge to zero. This zero current level is detected by a secondary winding on LPFC which is connected to the ZX pin. A positive-going edge exceeding the internal 2 V threshold (VZXTH+) signals the beginning of the off-time. A negative-going edge on the ZX pin falling below (VZXTH+ - VZXHYS) will occur when the LPFC current discharges to zero which signals the end of
Over-Voltage Protection (OVP)
Should over-voltage occur on the DC bus causing the VBUS pin to exceed the internal 4.3 V threshold (VBUSOV+), the PFC output is disabled (set to a logic `low'). When the DC bus decreases again causing the VBUS pin to
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IRS2166D(S)PbF
Ballast Design Equations
ILPFC
0
Note: The results from the following design equations can differ slightly from experimental measurements due to IC tolerances, component tolerances, and oscillator overand under-shoot due to internal comparator response time. Step 1: Program Deadtime
PFC pin
0
near peak region of rectified AC line
near zero-crossing region of rectified AC line
Fig. 12: On-time modulation near the zero-crossings decrease below the internal 4.0 V threshold (VBUSREG), a watch-dog pulse is forced on the PFC pin and normal PFC operation is resumed.
The deadtime between the gate driver outputs HO and LO is programmed with timing capacitor CT and an internal deadtime resistor RDT. The deadtime is the discharge time of capacitor CT from 3/5 VCC to 1/3 VCC and is given as:
t DT = CT 1475
or
[s]
(1)
Undervoltage Reset (UVR)
When the line input voltage is decreased, interrupted or a brown-out condition occurs, the PFC feedback loop causes the on-time of MPFC to increase in order to keep the DC bus constant. Should the on-time increase too far, the resulting peak currents in LPFC can exceed the saturation current limit of LPFC. LPFC will then saturate and very high peak currents and di/dt levels will occur. To prevent this, the maximum on-time is limited by limiting the maximum voltage on the COMP pin with an external zener diode DCOMP (Fig. 8). As the line input voltage decreases, the COMP pin voltage and therefore the ontime will eventually limit. The PFC can no longer supply enough current to keep the DC bus fixed for the given load power and the DC bus will begin to drop. Decreasing the line input voltage further will cause the VBUS pin to eventually decrease below the internal 3 V threshold (VBUSUV) (Fig. 9). When this occurs, VCC is discharged internally below VCCUV-, the IRS2166D enters UVLO mode and both the PFC and ballast sections are disabled (see State Diagram). The start-up supply resistor to VCC, together with the micro-power start-up current of the IRS2166D, determines the line input turnon voltage. This should be set such that the ballast turns on at a line voltage level above the undervoltage turn-off level, VCCUV+. It is the correct selection of the value of the supply resistor to VCC and the zener diode on the COMP pin that correctly program the on and off line input voltage thresholds for the ballast. With these thresholds correctly set, the ballast will turn off due to the 3.0 V undervoltage threshold (VBUSUV) on the VBUS pin, and on again at a higher liine input voltage (hysterisis) due to the supply resistor to VCC. This hysterisis will result in a proper reset of the ballast without flickering of the lamp, bouncing of the DC bus or re-ignition of the lamp when the DC bus is too low.
CT =
t DT 1475
[F]
(2)
Step 2: Program Run Frequency The final run frequency is programmed with timing resistor RT and timing capacitor CT. The charge time of capacitor CT from 1/3 VCC to 3/5 VCC determines the ontime of HO and LO gate driver outputs. The run frequency is therefore given as:
f RUN =
or
1 2 CT (0.51 RT + 1475) 1 - 2892 1.02 CT f RUN
[Hz]
(3)
RT =
[]
(4)
Step 3: Program Preheat Frequency The preheat frequency is programmed with timing resistors RT and RPH, and timing capacitor CT. The timing resistors are connected in parallel internally for the duration of the preheat time. The preheat frequency is therefore given as:
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IRS2166D(S)PbF
where,
f PH =
1 0.51 RT RPH 2 CT + 1475 R +R T PH
[Hz]
or
VBUS = DC bus voltage VAC MIN = Minimum rms AC input voltage (5) = PFC efficiency (typically 0.95) f MIN = Minimum PFC switching frequency at minimum
AC input voltage
RPH
1 1.02 C f - 2892 RT T PH = 1 RT - 1.02 C f - 2892 T PH
[] (6)
POUT =
Ballast output power
Step 2: Calculate peak PFC inductor current:
i PK =
2 2 POUT VAC MIN
[A]
(2)
Step 4: Program Preheat Time The preheat time is defined by the time it takes for the capacitor on pin CPH to charge up to 12 V. An internal current source of 3.6 A (ICPH) flows out of pin CPH. The preheat time is therefore given as: Note: The PFC inductor must not saturate at i PK over the specified ballast operating temperature range. Proper core sizing and air-gapping should be considered in the inductor design. Step 3: Calculate maximum on-time:
t PH = CPH 2.6e6
or
[s] [F]
(7) (8)
CPH = t PH 0.385e - 6
Step 5: Program Maximum Ignition Current
t ON MAX =
2 POUT LPFC 2 VAC MIN
[s]
(3)
The maximum ignition current is programmed with the external resistor RCS and an internal threshold of 1.20 V. This threshold determines the over-current limit of the ballast, which can be exceeded when the frequency ramps down towards resonance during ignition and the lamp does not ignite. The maximum ignition current is given as:
Step 4: Calculate maximum COMP voltage:
VCOMPMAX =
t ON MAX
0.9 E - 6
[V]
(4)
I IGN =
or
VCSTH + RCS VCSTH + I IGN
[A]
(9)
Step 5: Select zener diode DCOMP value:
DCOMP zener voltage VCOMPMAX
[] (10)
Step 6: Calculate resistor RSUPPY value:
[V]
(5)
RCS =
R SUPPLY =
VAC MIN
+ 10
PK
IQCCUV
[]
(6)
PFC Design Equations
Step1: Calculate PFC inductor value:
2 (VBUS - 2 VACMIN ) VAC MIN 2 f MIN POUT VBUS
LPFC =
[H]
(1)
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IRS2166D(S)PbF
CaseOutlines
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IRS2166D(S)PbF
16-Lead Tape & Reel
LOADED TAPE FEED DIRECTION
B
A
H
D F C
NOTE : CONTROLLING DIM ENSION IN M M
E G
CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60
16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062
F
D C E B A
G
H
REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724
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IRS2166D(S)PbF
ORDER INFORMATION
16-Lead PDIP IRS2166DPBF 16-Lead SOIC IRS2166DSPbF 16-Lead SOIC Tape & Reel IRS2166DSTRPbF
The SOIC-16 is MSL3 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105 Data and specifications subject to change without notice. 6/27/2006
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